Date: May 16th, 2012 – 9:00-16:00
Politecnico di Milano
Dipartimento di Elettronica ed Informazione
via Ponzio 34/5 – Seminar room (“Sala Seminari”) (directions)
It is widely accepted that one of the major challenges in electronic design automation (EDA) is design for manufacturing (DFM). In general terms DFM is defined as a set of techniques adopted to estimate, control, and improve the yield and robustness of a circuit before fabrication.
Yield loss in Integrated Circuits (ICs) can be decomposed into three factors: Defect density, Lithography-based, and Parametric-based. Defect density related yield loss is relatively controlled, but the other two components are increasingly important in nanoscale integrated circuits. Lithography-based yield loss is related to sub-wavelength lithography failures, causing either shorts or opens in the different layers. Parametric-based yield loss occurs because the manufactured chip does not meet a design parameter, like frequency or power dissipation. This last component of yield loss occurs because there is a large dispersion in circuit parameters due to process variations. It is important to note that a large part of process variations are also due to imperfections in lithography, and therefore, lithography-based problems impact both parametric yield loss and catastrophic lithography yield loss.
Optical lithography is the main process used in the Integrated Circuit (IC) industry to manufacture products. Unfortunately, optical lithography encounters serious limitations as we enter the Deep Sub-Micron era (DSM) which cause a serious decrease in yield and therefore jeopardises the advantages provided by technology scaling.
As we enter the Deep Sub-Micron era, optical lithography IC manufacturing processes need new solutions to manufacture products at low cost. Process variations pose many challenges for circuit design due to their effects on performance, power and yield. First, process variations decrease the predictability of circuit delay and power dissipation thus increasing the design time because of the difficulty of verifying and testing the resulting circuits. This circuit unpredictability has led to the concept of frequency binning, which is very costly in terms of performance (and hence, revenue) because many units perform worse than desired due to process variations. Process variations also reduce yield. This results in more time and investment required to increase yield to acceptable mass scale production levels, and therefore, in an increase of the time-to-market.
The seminar targets the optimisation of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels.
This seminar will present and discuss novel methodologies and associated design tools to help in the extraction of regularity at the architectural and structural level and automate the creation of regular compound cells. In particular, the cell creation methodology that will be presented employs Restricted Design Rules (RDR’s) and other regularity techniques at the geometrical level to maximise manufacturability and reduce systematic variations.
- Industrial design practice and EDA tools targeting regularity and variability for the future technologies. Nangate will discuss the role of cells libraries in the backend of this flow.
Leading Edge will refer to endeavors related to the design flows aimed at exploit regularity; what are the current tools and what are the missing tools; and how the missing tools can be integrated with an industrial design flow. Thales will discuss the impact of reliability and variability issues on the design of safety-critical systems. ST will address the impact of variability on advanced technology nodes and will discuss ways to use regularity to mitigate variability effects at these technologies.
- Advance design methodologies for future technologies at geometrical, circuit and logical level. This topic of the seminar will discuss three points. The first point addresses the regularity extraction at the structural level, as a way to analyse a specific design and find compound cells suitable for improving this design. Alternatives to map designs using compound gates are also discussed.
The second point discusses the creation of optimized transistor networks to implement compound cells. The creation of efficient transistor networks provides the link between compound gate candidate identification and the backend support given by cell creation. The third point discusses how to provide regular implementations at the geometrical levels for the discovered and generated transistor networks for compound gates.
Seminar Schedule – May 16th, 2012
- 9:15-9:30 Seminar introduction
Fabrizio Ferrandi (Politecnico di Milano)
- 9:30-10:00 Automated Layout Generation using the SYNAPTIC methodology
Martin Elhoj (Nangate A/S)
- 10:00-10:30 Safety-critical and mission-critical design challenges: the impact of future technologies
Arnaud Grasset (Thales Group)
- 10:30-11:00 break
- 11:00-11:30 Practical Approaches to Variability Handling
Nigel Woolaway (Leading Edge snc)
- 11:30-12:00 Variability in Advanced Nanometer Technologies: Challenges and Solutions
Cristiano Forzan (STMicroelectronics)
- 12:00-13:30 Lunch
- 13:30-14:00 On the Automatic Creation of Custom Standard-Cell Libraries
Christian Pilato (Politecnico di Milano)
- 14:00-14:30 Technology mapping with complex functions at cell and circuit level
Andre Reis (Universidade Federal do Rio Grande do Sul)
- 14:30-14:45 break
- 14:45-15:15 Regular layout to reduce process variations
Francesc Moll (Universitat Politècnica de Catalunya)
- 15:15-15:45 SYNAPTIC Layout Generation and Design Synthesis Demonstration
Guilherme Schlinker (Nangate A/S)
Seminar Registration Form link