EU-funded SYNAPTIC project delivers state of the art design synthesis tool flow
Copenhagen, Denmark — March 13, 2012
An EDA industry consortium, supported by the European Union’s Seventh Framework Programme, reports the release of its design synthesis tool flow after the second year of the three-year project.
The SYNAPTIC research project includes eight partner organisations from across Europe who have joined forces to develop new regularity-centric design methods and related EDA tools. The goal is to reduce limitations in physical implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography.
At the heart of the SYNAPTIC project is the development of regularity-aware synthesis methodologies, first at the architectural level, then at the synthesis level, and finally in layout generation and the subsequent integration of the new methods into EDA tools.
State-of-the-art Design Synthesis Tool Flow
Martin Elhøj, SYNAPTIC Project Coordinator and VP R&D with NanGate, explains that the consortium has completed the integration of new state of the art design synthesis algorithms and methodologies developed in the project into a prototype EDA tool build on top of Nangate’s Design Optimizer product. The synthesis tool identifies functionality which, if added to the base synthesis library, enables further optimisation of critical design metrics. The additional functionality is then automatically implemented as new standard cells using the SYNAPTIC RDR layout generation tool based on Nangate’s Library Creator product. The design specific functions are created from highly optimized Boolean expressions aiming to reduce transistor count when compared to the same functionality implemented using multiple standard cells. This approach has consistently shown more than 20% reduction in transistor count for medium size compound cells and the design resynthesis utilizing the extended cell set provides area improvements not available with current EDA tools while maintaining other critical design metrics. In this way the impact on area imposed by Restricted Design Rules is reduced thus enabling the creation of competitive designs employing regularity techniques to reduce variability and improve yield. Although the tools are in the prototype stage they already demonstrate very good results and further optimizations are the target of the third and final year of the project.
Layout Styles and Restricted Design Rules effectively reduces Variability
The project has developed two unique layout styles and sets of restricted design rules; (1) ALARC for strict 1D routing and (2) 2D Gridded allowing 2D M1 routing while keeping all other layers 1D. The two structures have been demonstrated to significantly reduce the variations of drawn transistor length and width when compared to traditional layout styles. This reduces the overall variability of a design, and thus enables designers to reduce the guard bands that have become common in today’s design methodology.
To confirm that the proposed RDR rules and layout styles are feasible candidates to be deployed in industrial designs where SRAM is commonplace, the consortium has designed three SRAM bit cell layouts and compared the Figure of Merits (FOM) against a state-of-the-art high density SRAM cell. The results confirm that it is indeed feasible to create SRAM cells with comparable FOM using the regular layout styles.
Measurement of layout regularity is a critical aspect in regularity-centric design creation and to quickly assess the level of regularity without the need for compute intensive and expensive litho simulation tools, the consortium has developed a fast regularity metric; ARMLE (Algorithm of Regularity Metric for Layout Evaluation). This metric enables the qualitative comparison of different layout styles with respect to regularity.
Meet SYNAPTIC at DATE2012 and DAC2012
SYNPATIC project is the co-organizer of the Friday workshop, VAMM, at DATE 2012 in Dresden, Germany on March 16, 2012. The workshop will focus on design techniques to counteract the problem of variability. Techniques may range from the device level, to layout design, to architecture design. They include the use of redundancy, regularity and reconfiguration at different description levels.
The SYNAPTIC project will showcase its design synthesis tool flow during DAC 2012 in San Francisco, CA. from June 4 to June 6 2012.
Consortium partners include design optimization company Nangate, Europe’s largest IDM, STMicroelectronics; Thales (France), which is the European global technology leader for the aerospace, space, defence, security and transportation markets; and imec (Belgium), which performs world-leading research in nanoelectronics. Three leading universities, Politecnico di Milano (Italy), Universitat Politècnica de Catalunya (Spain) and Universidade Federal do Rio Grande do Sul (Brazil) bring significant and highly specialised technology contributions to the joint research. The final partner, Leading Edge, is participating as a consultancy company specialising in the introduction of innovative EDA technologies to the European marketplace.