The influence of process variations is becoming extremely critical for nanoCMOS technology nodes, due to geometric tolerances and manufacturing non-idealities (such as edge or surface roughness, or the fluctuation of the number of doping atoms). As a result, production yields and figures of merit of a circuit such as performance, power, and reliability have become extremely sensitive to uncontrollable statistical process variations. Although some kind of variability has always existed and been taken into account for designing integrated circuits, the largest impact of variability and the greater influence of random or spatial aspects are setting up a completely new challenge. On top of those difficulties, the deficiency of design techniques and EDA methodologies for tackling PVs makes that challenge even more critical. Variability has a huge economic impact in terms of yield loss or overdesign that is increasing with each technology generation. Without design countermeasures to reduce the impact of process variations, the cost advantage of technology scaling will be overrun by losses due to an increasing gap between designed and actual performances and therefore technology scaling will not be sustainable.
A one-day Friday Workshop in conjunction with DATE 2012 (Dresden, Germany) will be celebrated addressing these topics on March 16, 2012. The workshop will focus on design techniques to counteract the problem of variability. Techniques may range from the device level, to layout design, to architecture design. They include the use of redundancy, regularity and reconfiguration at different description levels.
Additional information can be found at: http://www.synaptic-project.eu/vamm12
VAMM is connected with the following projects: