Press release summarising first year of activity

EU-funded SYNAPTIC project claims advances in regularity

Copenhagen, Denmark – January 12, 2011

An EDA industry consortium, supported by the European Union’s Seventh Framework Programme, reports tangible progress after the first year of the three-year project.

The SYNAPTIC research project includes eight partner organisations from across Europe who have joined forces to develop new microprocessor design methods and related EDA tools. The goal is to reduce limitations in physical implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography.

At the heart of the SYNAPTIC project is the development of regularity-aware synthesis methodologies, first at the architectural level, then at the synthesis level, and finally in layout generation and integration of the new methods into EDA tools.

Structural level regularity

Martin Elhøj, SYNAPTIC Project Coordinator with Nangate A/S in Herlev, Denmark, explains that the consortium examined regular structures in computing architectures and engines, which led to the selection of two industrial test benches that will be used by the project to evaluate the benefits of new synthesis and layout generation algorithms and methods.

Efforts at the synthesis level have focused on developing new regularity-aware synthesis methodologies that, given an application represented at RTL in Verilog or VHDL, (1) transforms the original netlist preserving the RTL inherent regularity, (2) identifies complex Boolean functions and regular logic structures, and (3) covers the original netlist with the identified structures.

Work is progressing with the development of tools and methodologies that extract regularity at the structural level and use these results to drive the optimised generation of application-specific custom Boolean functions. This approach will overcome the limitations of traditional synthesis methods that rely on a standard library alone.

New flow for layout generation

An innovative layout generation flow was established that enables the automatic generation of standard cell layouts with configurable levels of regularity. Based on this flow, the consortium has developed two unique cell architectures that take lithography effects into consideration and thus enhance manufacturability and aim at reducing variability. The two architectures are (1) Via-Configurable Transistor Array (VCTA), an extremely regular fabric, and (2) ALARC (Adaptive Lithography Aware Regular Cell), a more conventional regular cell with design restrictions imposed by lithography limitations.

To further increase the competitiveness of the regular layouts, the consortium has achieved significant improvements in the netlist synthesis step, leading to reduced transistor count and thus improved cell area.

The benefits of the regular design methodology will be evaluated at several levels, including lithography evaluation for both logic and SRAM. In particular, a litho process variability aware methodology to characterise SRAM variability was defined.

An integral part of the project is the exploitation of the developed methods and algorithms in commercial EDA tools and to ensure that the methodology can be integrated into commercial design flows. Significant progress has been made by the integration of the innovative regular layout generation flow into a SYNAPTIC variant of the Nangate Library Creator™. Nangate anticipates that the methods developed in the project’s first year can be exploited in its commercial tools in the very near term.

The project’s successes to date have been disseminated in several papers presented at major conferences, including DATE2010, SBCCI2010, ICCD2010, ESREF2010 and ISVLSI2010, and published by journals such as JOLPE, Microelectronics Journal, Microelectronics Reliability and SBC RBIE. In February 2011, the consortium is organising the ERDIAP workshop in conjunction with ARCS (Architecture of Computing Systems) in Como, Italy.

Consortium partners include design optimisation company Nangate, Europe’s largest IDM, STMicroelectronics; Thales (France), which is the European global technology leader for the aerospace, space, defence, security and transportation markets; and imec(Belgium), which performs world-leading research in nanoelectronics. Three leading universities, Politecnico di Milano (Italy), Universitat Politècnica de Catalunya (Spain) and Universidade Federal do Rio Grande do Sul (Brazil) bring significant and highly specialised technology contributions to the joint research. The final partner, Leading Edge, is participating as a consultancy company specialising in the introduction of innovative EDA technologies to the European marketplace.

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