EU funded microelectronics project launched to enhance lithography-based yield
Copenhagen, Denmark, February 11, 2010 —
Supported by funding from the European Union’s Seventh Framework Programme, a consortium of eight leading institutions has launched a joint microelectronics research project aiming to develop innovative design methods and related EDA tools which remove the limitations in physical implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography. The Synaptic consortium is composed of eight leading institutions, including four European technology companies, a European world-leading research institute in the field of nanoelectronics, and three academic institutions, two from Europe and one from Brazil.
Through use of a more restrictive set of layout patterns with predictable layout neighbourhood, variability caused by the physical limitations of current industrial lithography techniques can be reduced and manufacturing yield can be improved. An additional benefit of this approach is that it eases RET computation and hence reduces mask generation complexity. However, in particular for implementation of random logic with state-of-the-art automated implementation methodologies, the layout restrictions lead to loss of density of the logic cell libraries and a reduced block-level gate density when compared with traditional methodology utilising cell libraries with more complex layout patterns. For this reason, complex patterned logic cells followed by advanced mask processing steps have continued to be the dominating approach.
With the introduction of advanced process nodes at 32nm and below, new and significant layout restrictions lead to a more regular layout style being applied for the fundamental logic cells. The trend for more regular layout will continue as scaling advances. To enable technology scaling to remain attractive, it is necessary to counter the negative effects of regularity restrictions on logic density. It is therefore critically important to focus research efforts on exploring and developing innovative design techniques and methodologies, along with associated CAD tools and logic cell libraries, which remove the limitations in design implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography.
The consortium behind the Synaptic project spans a range of technology companies and research institutions, each with a unique specialisation, allowing them to set up a unique joint research project aiming to develop a revised design methodology in which the concept of regularity is propagated through all abstraction levels: architectural, logic and physical layout.
From an architectural point of view, the advantages of the proposed methodology include the ability to exploit step and repeat approaches employing complex logic cells and complex logic building blocks, thus providing greater predictability of design performance and enabling comprehensive early architecture exploration. Reliance upon complex logic cells and logic building blocks realised by regular layout patterns reduces sensitivity to process variations, improves performance predictability and enables tighter design margins.
From a logic design point of view, the advantages include the creation of logic cell libraries targeted to design requirements, thus improving performance and performance predictability.
From a physical design point of view, this approach will enable the use of lower-cost lithography techniques as compared to complex patterned logic cell approaches while achieving the same yield. This makes it cost-effective to use more advanced lithography techniques on large SoC designs, thus enabling the use of more advanced semiconductor technologies. Layout regularity will further increase the predictability of the design as well as reducing excessively small CD transistors which add to leakage problems.
Nangate A/S, based in Copenhagen, Denmark is the project coordinator. According to Nangate’s CEO, Ole Chr. Andersen, participation in the project “will enable Nangate to further strengthen and escalate our existing technology partnership and customer relations that focus on introducing regular layout optimised capabilities to our present range of advanced cell library and design optimisation EDA tools”.
Consortium partners include Europe’s largest IDM, STMicroelectronics; Thales (France), which is the European global technology leader for the aerospace, space, defence, security and transportation markets; and imec (Belgium), which performs world-leading research in nanoelectronics. Three leading universities, Politecnico di Milano (Italy), Universitat Politècnica de Catalunya (Spain) and Universidade Federal do Rio Grande do Sul (Brazil) will bring significant and highly specialised technology contributions to the joint research. The final partner, Leading Edge, is participating in its capacity as a consultancy company specialising in the introduction of innovative EDA technologies to the European marketplace.
About Nangate A/S:
Nangate is an innovative EDA software and IP provider, focussed on selling its EDA products and services to IDMs, foundries and fabless semiconductor companies in Europe and across the world. Through the merger of physical synthesis and cell library creation, the company provides a unique alternative to one-size-fits-all standard-cell libraries, and offers a low-risk alternative to full-custom chip design. Nangate is the only partner that can provide the software base for automatic cell layout generation and netlist synthesis which is central to the project.
Nangate employs a world-class team of EDA tool developers and design flow experts in three product development facilities – Copenhagen (Denmark), Moscow (Russia) and Porto Alegre (Brazil). Nangate is privately owned with venture capital backing, and was incorporated in Denmark in 2004.
STMicroelectronics is a global leader serving customers across the spectrum of electronics applications with innovative semiconductor solutions. ST aims to be the undisputed leader in multimedia convergence and power applications, leveraging its vast array of technologies, design expertise and combination of intellectual property portfolio, strategic partnerships and manufacturing strength. In 2009, the Company’s net revenues were $8.51 billion. Further information on ST can be found at www.st.com.
Thales develops strategic capabilities in component, software and system engineering and architectures through its Research & Technology (R&T) organisation. This organisation focuses on critical information systems, processing, control and cognitive systems, and autonomous systems. A key mission of Thales R&T centres is bi-directional transfer between scientific research and the corresponding businesses. Benefiting from its presence and visibility on the international scene in advanced sciences, technology and software, Thales R&T is perceived as a valuable partner of the best research centres (academic or industrial) through recognised scientists and research engineer participation in collaborative projects.
Thales Research & Technology’s Information Science and Technology Group is able to develop innovative solutions along the information chain exploiting sensors data, through expertise in computational architectures in embedded systems, typically suitable for autonomous system environments, mathematics and technologies for decision involving information fusion and cognitive processing, and cooperative technologies including man system interaction.
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China and Japan. Its staff of more than 1,650 people includes over 550 industrial residents and guest researchers. In 2008, imec’s revenue (P&L) was 270 million euro. Further information on imec can be found at www.imec.be.
Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (imec vzw supported by the Flemish Government), imec the Netherlands (Stichting imec Nederland, part of Holst Centre which is supported by the Dutch Government) and imec Taiwan (imec Taiwan Co.).
About Politecnico di Milano:
The Politecnico di Milano is one of the largest Italian engineering universities, ranked among the best fifteen technology universities in Europe in the Times Higher Education-QS World University Rankings. This project will involve personnel of the Embedded systems design and design methodologies of the Dipartimento di Elettronica e Informazione, composed of 4 full professors, 6 associate professors, and a number of assistant professors and PhD students. The research group has long been active in the field of designing computer architectures and developing methodologies and prototype tools to support the automation of different phases of design of advanced embedded systems.
About Universitat Politècnica de Catalunya:
UPC is one of the main technical universities in Spain. It is specialised in the areas of engineering, science and architecture. It has around 30,000 undergraduate students and 4,000 graduate students (PhD and Master). It has a teaching staff of nearly 3,000. The UPC participation in the Synaptic project is through the research group “High Performance Integrated Circuits and Systems Design Group” (HIPICS), in the Department of Electronic Engineering. With more than 15 years of experience, this research group has covered several areas of research: design and test techniques for integrated circuits, energy harvesting, design of CMOS RF circuits, and design techniques for integrated circuits tolerant to noise and process variations.
About Universidade Federal do Rio Grande do Sul:
UFRGS is one of the largest Brazilian universities, ranking in top positions for graduate and undergraduate courses in Computer Science, Computer Engineering and Microelectronics. This project will involve personnel of the Group of Computational Tools for Integrated Circuit Design of the Instituto de Informática, composed of 2 professors, and around 15 researchers divided into Post-doc grantees, PhD students, MsC1 students and undergraduate students. The research group has long been active in the field of computational tools for integrated circuit design, especially at the cell level where the group developed a unique competence in switch theory and transistor network generation and evaluation.
About Leading Edge:
Leading Edge is a privately held company specialising in the introduction of innovative EDA technologies to the European marketplace. Leading Edge was formed in 2005 and benefits from the considerable EDA experience gained by the founders while working for major players in the EDA arena such as Synopsys, Mentor Graphics and Magma Design Automation. Leading Edge provides technical consulting and commercial services to a number of European and US-based EDA startups. Leading Edge also provides training courses on various design-related topics and is a certified training center for Mentor Graphics and a member of the Altera Training Partner Program.
For further information on the Synaptic project, contact:
Mr. Henrik Pallisgaard
DK-2730 Herlev, Denmark
Tel: +45 4452 1407
Web site: www.synaptic-project.eu